--------------------------------------------------------------------- -- -- Fichero: -- lab9.vhd 27/4/2017 -- -- (c) J.M. Mendias -- Diseño Automático de Sistemas -- Facultad de Informática. Universidad Complutense de Madrid -- -- Propósito: -- Laboratorio 9 -- -- Notas de diseño: -- --------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; entity lab9 is port( rstPb_n : in std_logic; osc : in std_logic; rec_n : in std_logic; play_n : in std_logic; incVol_n : in std_logic; decVol_n : in std_logic; led : out std_logic; upSegs : out std_logic_vector(7 downto 0); leftSegs : out std_logic_vector(7 downto 0); rightSegs : out std_logic_vector(7 downto 0); mclk : out std_logic; sclk : out std_logic; lrck : out std_logic; sdti : out std_logic; sdto : in std_logic; clkOutFb : in std_logic; clkOut : out std_logic; cke : out std_logic; cs_n : out std_logic; ras_n : out std_logic; cas_n : out std_logic; we_n : out std_logic; ba : out std_logic_vector( 1 downto 0); sAddr : out std_logic_vector(12 downto 0); sData : inout std_logic_vector(15 downto 0); dqmh : out std_logic; dqml : out std_logic ); end lab9; ------------------------------------------------------------------- library ieee; use ieee.numeric_std.all; use work.common.all; architecture syn of lab9 is constant SAMPLESNUM : natural := 48_828*2*60; signal ready, rstInit_n : std_logic; signal clk, rst_n : std_logic; signal recSync_n, recDeb_n, recFall : std_logic; signal playSync_n, playDeb_n, playFall : std_logic; signal incVolSync_n, incVolDeb_n, incVolFall : std_logic; signal decVolSync_n, decVolDeb_n, decVolFall : std_logic; signal inSample, outSample : std_logic_vector (15 downto 0); signal inSampleRdy, outSampleRqt : std_logic; signal wr, rd, opBegun : std_logic; signal hDIn, hDOut : std_logic_vector(15 downto 0); signal hAddr : std_logic_vector(23 downto 0); signal recAddr, playAddr : unsigned (23 downto 0); signal vol : unsigned(3 downto 0); signal secHigh, secLow : unsigned (3 downto 0); type states is (initial, recording, writeSample, waiting, playing, readSample); signal state : states; begin rstInit_n <= rstPb_n and ready; resetSyncronizer : synchronizer generic map ( STAGES => 2, INIT => '0' ) port map ( rst_n => rstInit_n, clk => clk, x => '1', xSync => rst_n ); clkDesckewer : desckewer generic map ( FREQ => 50_000 ) port map ( clkIn => osc, intClk => clk, extClk => clkOut, extClkFb => clkOutFb, ready => ready ); ------------------ recSynchronizer : synchronizer generic map ( STAGES => 2, INIT => '1' ) port map ( rst_n => rst_n, clk => clk, x => rec_n, xSync => recSync_n ); recDebouncer : debouncer generic map ( FREQ => 50_000, BOUNCE => 50 ) port map ( rst_n => rst_n, clk => clk, x_n => recSync_n, xDeb_n => recDeb_n ); recEdgeDetector : edgeDetector port map ( rst_n => rst_n, clk => clk, x_n => recDeb_n, xFall => recFall, xRise => open ); playSynchronizer : synchronizer generic map ( STAGES => 2, INIT => '1' ) port map ( rst_n => rst_n, clk => clk, x => play_n, xSync => playSync_n ); playDebouncer : debouncer generic map ( FREQ => 50_000, BOUNCE => 50 ) port map ( rst_n => rst_n, clk => clk, x_n => playSync_n, xDeb_n => playDeb_n ); playEdgeDetector : edgeDetector port map ( rst_n => rst_n, clk => clk, x_n => playDeb_n, xFall => playFall, xRise => open ); incVolSynchronizer : synchronizer generic map ( STAGES => 2, INIT => '1' ) port map ( rst_n => rst_n, clk => clk, x => incVol_n, xSync => incVolSync_n ); incVolDebouncer : debouncer generic map ( FREQ => 50_000, BOUNCE => 50 ) port map ( rst_n => rst_n, clk => clk, x_n => incVolSync_n, xDeb_n => incVolDeb_n ); incVolEdgeDetector : edgeDetector port map ( rst_n => rst_n, clk => clk, x_n => incVolDeb_n, xFall => incVolFall, xRise => open ); decVolSynchronizer : synchronizer generic map ( STAGES => 2, INIT => '1' ) port map ( rst_n => rst_n, clk => clk, x => decVol_n, xSync => decVolSync_n ); decVolDebouncer : debouncer generic map ( FREQ => 50_000, BOUNCE => 50 ) port map ( rst_n => rst_n, clk => clk, x_n => decVolSync_n, xDeb_n => decVolDeb_n ); decVolEdgeDetector : edgeDetector port map ( rst_n => rst_n, clk => clk, x_n => decVolDeb_n, xFall => decVolFall, xRise => open ); ------------------ codecInterface : iisInterface generic map( WIDTH => 16 ) port map( rst_n => rst_n, clk => clk, leftChannel => open, inSample => inSample, inSampleRdy => inSampleRdy, outSample => outSample, outSampleRqt => outSampleRqt, mclk => mclk, sclk => sclk, lrck => lrck, sdti => sdti, sdto => sdto ); volShifter : outSample <= ...; hDIn <= inSample; hAddr <= ... when wr='1' else ...; wr <= ... when state=... else ...; rd <= ... when state=... else ...; ram : sdramController generic map( FREQ => 50_000, PIPE_EN => false, MAX_NOP => 10_000, MULTIPLE_ACTIVE_ROWS => false, ENABLE_REFRESH => true, DATA_WIDTH => 16, NROWS => 8192, NCOLS => 512, HADDR_WIDTH => 24, SADDR_WIDTH => 13 ) port map( clk => clk, lock => ready, rst => not(rst_n), rd => rd, wr => wr, hAddr => hAddr, hDIn => hDIn, hDOut => hDOut, rdPending => open, opBegun => opBegun, earlyOpBegun => open, rdDone => open, done => open, cke => cke, ce_n => cs_n, ras_n => ras_n, cas_n => cas_n, we_n => we_n, ba => ba, sAddr => sAddr, sData => sData, dqmh => dqmh, dqml => dqml ); fsmd : process (rst_n, clk) begin if rst_n='0' then recAddr <= (others => '0'); playAddr <= (others => '0'); state <= initial; elsif rising_edge(clk) then ...; end if; end process; ------------------ volCounter : process (rst_n, clk) begin ... end process; secCounter : process (rst_n, clk) constant MAXVALUE : natural := 50_000_000-1; variable count, countReg : natural range 0 to MAXVALUE; variable secHighReg, secLowReg : unsigned(3 downto 0); begin ... end process; ------------------ led <= '1' when state=recording or state=writeSample else '0'; upConverter : bin2segs port map ( bin => std_logic_vector(vol), dp => '0', segs => upSegs ); leftConverter : bin2segs port map ( bin => std_logic_vector(secHigh), dp => '0', segs => leftSegs ); rigthConverter : bin2segs port map ( bin => std_logic_vector(SecLow), dp => '0', segs => rightSegs ); end syn;