---------------------------------------------------------------------
--
--  Fichero:
--    lab12.vhd  28/2/2024
--
--    (c) J.M. Mendias
--    Diseño Automático de Sistemas
--    Facultad de Informática. Universidad Complutense de Madrid
--
--  Propósito:
--    Laboratorio 12
--
--  Notas de diseño: 
--
---------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

entity lab12 is
  port ( 
    clk      : in  std_logic;
    filterOn : in  std_logic;
    sel      : in  std_logic;
    thold    : in  std_logic_vector (3 downto 0);
    -- VGA side
    hSync    : out  std_logic;
    vSync    : out  std_logic;
    RGB      : out  std_logic_vector(11 downto 0);
    -- Camera side    
    pClk     : in  std_logic;
    xClk     : out std_logic;
    cvSync   : in  std_logic;
    hRef     : in  std_logic;
    cData    : in  std_logic_vector(7 downto 0);
    sioc     : out std_logic;
    siod     : out std_logic;
    pwdn     : out std_logic;
    rst_n    : out std_logic
  );
end lab12;

library ieee;
use ieee.numeric_std.all;
use work.common.all;

architecture syn of lab12 is
    
  component frameBuffer
    port (
      clka  : in  std_logic;
      wea   : in  std_logic_vector (0 downto 0);
      addra : in  std_logic_vector (16 downto 0);
      dina  : in  std_logic_vector (3 downto 0);
      clkb  : in  std_logic;
      addrb : in  std_logic_vector (16 downto 0);
      doutb : out std_logic_vector (3 downto 0)
    );
  end component;
  
  component videoEdgeDetector is
    port ( 
      -- host side
      clk      : in  std_logic;    
      start    : in  std_logic;
      filterOn : in  std_logic;
      sel      : in  std_logic;
      thold    : in  std_logic_vector (3 downto 0);
      -- frame buffers side
      y        : out std_logic_vector (7 downto 0);
      x        : out std_logic_vector (8 downto 0);
      dataIn   : in  std_logic_vector (3 downto 0);
      dataOut  : out std_logic_vector (3 downto 0);
      dataRdy  : out std_logic
    );
  end component;
   
  constant PIXELSxLINE : natural := 640/2;
  constant LINESxFRAME : natural := 480/2;
  
  constant FREQ_KHZ : natural := 100_000;  -- frecuencia de operacion en KHz
  constant VGA_KHZ  : natural := 25_000;   -- frecuencia de envio de pixeles a la VGA en KHz
  constant FREQ_DIV : natural := FREQ_KHZ/VGA_KHZ; 

  constant BAUDRATE : natural := 400_000;   -- velocidad de comunicacion con el interfaz SBBC
  
  signal progRdy, rec, xclkRdy, frameRdy : std_logic;

  signal wrData, rdData : std_logic_vector(3 downto 0);
  
  signal color : std_logic_vector(11 downto 0); 

  signal grey, dataOutFilter, dataInFilter, dataInVga : std_logic_vector(3 downto 0);
  signal dataRdyCam, dataRdyFilter : std_logic;
   
  signal yCam, yVga : std_logic_vector(8 downto 0);
  signal xCam, xVga : std_logic_vector(9 downto 0);

  signal yFilter : std_logic_vector(7 downto 0);
  signal xFilter : std_logic_vector(8 downto 0);

  signal videoInWrAddr, videoInRdAddr, videoOutWrAddr, videoOutRdAddr : std_logic_vector(16 downto 0);

  signal pingDataInFilter, pongDataInFilter, pingDataInVga, pongDataInVga : std_logic_vector(3 downto 0);

  signal pingVideoInWea, pongVideoInWea, pingVideoOutWea, pongVideoOutWea : std_logic;

  signal ping : std_logic := '1';
  
  function xy2addr( x : std_logic_vector; y : std_logic_vector ) return std_logic_vector is
    variable xVal   : unsigned(x'range); 
    variable yVal   : unsigned(y'range);
    variable result : unsigned(16 downto 0);
  begin  
    xVal   := unsigned( x );
    yVal   := unsigned( y );
    result := yVal*to_unsigned(PIXELSxLINE,9) + resize( xVal, 17 );
    return std_logic_vector( result );
  end function; 
      
begin
 
  rst_n <= '1';
  pwdn  <= '0';

  xclkGenerator : freqSynthesizer
    generic map ( FREQ_KHZ => FREQ_KHZ, MULTIPLY => 1, DIVIDE => 4 )
    port map ( clkIn => clk, rdy => xclkRdy, clkOut => xclk );
    
  ------------------  

  programmer : ov7670programmer
    generic map ( FREQ_KHZ => FREQ_KHZ, BAUDRATE => BAUDRATE, DEV_ID => "0100001" )
    port map ( clk  => clk, rdy => progRdy, sioc => sioc, siod => siod );  
 
  ------------------  
   
  rec <= progRdy and xclkRdy;
 
  videoIn: ov7670reader 
    port map ( clk => clk, rec => rec, x => xCam, y => yCam, dataRdy => dataRdyCam, data => color, frameRdy => frameRdy, pClk => pClk, cvSync => cvSync, hRef => hRef, cData => cData );
       
  converter: rgb2grey
    port map ( rgb => color, grey => grey );
       
  process( clk )
  begin
    if rising_edge( clk ) then
      if frameRdy='1' then
        ping <= not ping;
      end if;
    end if;
  end process;
        
  ------------------  
    
  pingVideoInWea <= ...;   
  pongVideoInWea <= ...;
  videoInWrAddr  <= xy2addr( ... ); 
  videoInRdAddr  <= xy2addr( ... );
  
  pingVideoInMemory : frameBuffer 
    port map ( clka => clk, addra => videoInWrAddr, dina => grey, wea(0) => pingVideoInWea, clkb => clk, addrb => videoInRdAddr, doutb => pingDataInFilter );

  pongVideoInMemory : frameBuffer 
    port map ( clka => clk, addra => videoInWrAddr, dina => grey, wea(0) => pongVideoInWea, clkb => clk, addrb => videoInRdAddr, doutb => pongDataInFilter );
  
  dataInFilter <= ...;
  
  ------------------  
     
  filter : videoEdgeDetector 
    port map ( clk => clk, start => frameRdy, filterOn => filterOn, sel => sel, thold => thold, y => yFilter, x => xFilter, dataIn => dataInFilter, dataOut => dataOutFilter, dataRdy => dataRdyFilter );
        
  ------------------  
  
  pingVideoOutWea <= ...;        
  pongVideoOutWea <= ...;
  videoOutWrAddr  <= xy2addr( ... ); 
  videoOutRdAddr  <= xy2addr( ... );
  
  pingVideoOutMemory : frameBuffer 
    port map ( clka => clk, addra => videoOutWrAddr, dina => dataOutFilter, wea(0) => pingVideoOutWea, clkb => clk, addrb => videoOutRdAddr, doutb => pingDataInVga );

  pongVideoOutMemory : frameBuffer 
    port map ( clka => clk, addra => videoOutWrAddr, dina => dataOutFilter, wea(0) => pongVideoOutWea, clkb => clk, addrb => videoOutRdAddr, doutb => pongDataInVga );

  dataInVga <= ...;
    
  ------------------  

  videoOut : vgaRefresher
    generic map ( FREQ_DIV => FREQ_DIV )
    port map ( clk => clk, line(9) => open, line(8 downto 0) => yVga, pixel => xVga, R => dataInVga, G => dataInVga, B => dataInVga, hSync => hSync, vSync => vSync, RGB => RGB );
            
end syn;