RISC-V: Architecture and Design based on Commercial VeeR Cores on FPGA

The module covers RISC-V architecture and practical programming in C and assembly. Students create projects for the RVfpga system, practice both languages, and complete a final image-processing project combining C and assembly with added extensions.

This module covers the RVfpga I/O system, including Verilog basics, GPIO and peripheral expansion, displays and counters, interrupt-based I/O, and serial bus communication with practical use of onboard devices like the accelerometer.

This module introduces the microarchitecture of the VeeR EL2 and VeeR EH1 processors, covering pipeline organization, instruction execution, processor configuration, and performance analysis. It also presents advanced techniques such as superscalar execution and branch prediction, along with custom instructions and key memory hierarchy components.

This final, shorter module introduces SoC design. Students build the RVfpga SoC from scratch by connecting the VeeR EH1 core, interconnection network, and peripherals using Vivado Block Design. They then run the system on the Nexys A7 board, load the Zephyr RTOS, and execute a TensorFlow Lite application.