Functional Verification of Digital Integrated Circuits using UVM Methodology

Facultad de Informática. Universidad Complutense de Madrid

Details

The course

22,5 contact hours

May 11, 2026 - June 26, 2026

Hybrid modality

6 face-to-face sessions. Rest online

6 ECTS

Total workload of 45 hours (22,5 face-to-face and 22,5 online)

Functional Verification of Digital Integrated Circuits

This course provides an introduction to advanced verification methodologies for digital integrated circuits using the Universal Verification Methodology (UVM). It assumes that participants have a prior understanding of hardware description languages and includes a concise overview of SystemVerilog before focusing on the development and implementation of UVM-based verification environments.

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Universidad Complutense de Madrid OpenChip Project

Modules

Synthesizable SystemVerilog

  • Main features of the SystemVerilog language
  • Structure of a SystemVerilog model
  • Basic data types and operators
  • Procedural blocks
  • Procedural statements
  • Hierarchical and modular design
  • Definition and implementation of interfaces

Metrics and Methodologies for System Verification

  • Methods for validating a digital design
  • Formal verification
  • Property-based verification
  • General strategies for functional verification
  • Verification metrics and coverage
  • Code coverage: types and analysis

SystemVerilog in Verification

  • Introduction to the use of SystemVerilog in functional verification
  • Advanced data types and dynamic data structures
  • Procedural statements applied to verification
  • Clocking blocks and stimulus synchronization
  • SystemVerilog Assertions (SVA)
  • Object-oriented programming in SystemVerilog
  • Random stimulus generation
  • Communication between concurrent processes
  • Functional coverage

Testbench Architecture

  • Basic rules and principles for building testbenches
  • Testbench structure and associated notation
  • Testbench architecture: components, hierarchy, and data flow

Universal Verification Methodology (UVM)

  • Fundamentals of the UVM methodology
  • Simulation process in UVM environments
  • Communication mechanisms in UVM
  • UVM structural elements
  • Factory mechanism and dynamic instantiation management
  • Configuration and management of the configuration database

Faculty

Óscar Garnica

Óscar Garnica

Associate Professor at the Universidad Complutense de Madrid with over 20 years of experience in ASIC and FPGA design and verification. He combines academic activity with hands-on industrial expertise as a former ASIC Design Engineer at Lucent Bell Labs Innovations, Agere Systems, and LSI. He has led multiple publicly funded R&D projects and industrial collaborations (Indra, Airbus, CRISA, KDPOF) focused on advanced FPGA architectures and functional verification methodologies.

Keyfacts

Price

120€/

  • 12 students per edition.

Duration

6 ECTS/

  • 22,5 hours face-to-face and 22,5 hours online.

Collaboration

openchip/

  • Training designed in collaboration with openchip.

Location

FDI/

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More information

More information

More information and registration on the Formación Permanente page of the Universidad Complutense de Madrid, including administrative information to apply for the master’s program, enroll, apply for scholarships, etc. can be found on the master’s page of the Faculty of Computer Science

Facultad de Informática. Universidad Complutense de Madrid. Ciudad Universitaria. C/ Profesor José García Santesmases, 9, Madrid, 28040
Coordinator: Oscar Garnica. Email: ogarnica@ucm.es